The invention concerns a static frequency divider with a divider ratio which can be switched over, for use in the extremely high frequency range.
Binary frequency dividers are a crucial component in frequency synthesizers as are employed in integrated transmitting and receiving circuits.
Usually, frequency dividers comprise a synchronous binary divider and logic blocks connected at the upstream side, for setting the desired division ratio. Circuit arrangements of that kind are described in IEICE Trans. Electron, Vol. E 80-C, No.2, pages 314-319, Feb. 1997 and IEICE Trans. Electron, Vol. E 75-C, No.10, 5. 1115-1120, Oct. 1992. In that respect the delay caused by the logic blocks represents a fundamental speed limitation as the logical decision must be taken before the following clock input signal is received. That additional delay limits the maximum clock frequency. In addition the necessary driver and logic circuits cause relatively high power losses as the signal levels used are only in the range of between 200 and 500 mV and corresponding level lifting is required.
An attempt to overcome that limitation is based on the principle of phase rotation selection which permits the design of asynchronous high speed circuits with a division ratio of 2, see IEEE Journal of Solid State Circuits, Vol. 31, No. 7, 5.890-897, July 1996. Admittedly that principle overcomes the limiting delay, but in this case also additional level drivers and logic circuits with corresponding power losses are required.
DE 198 48 300 also describes a circuit arrangement for a static frequency divider with a divider ratio which can be switched over, for which no additional level drivers and logic circuits are required. In this case, two divider D-type flip-flops which are modified by additional input transistor pairs and switching transistors are provided in a divider stage. A change-over switching device is connected in parallel to the two control inputs of the divider D-type flip-flops. When the operating current of the pairs of input transistors is switched over, precisely one input clock period is suppressed and thus the corresponding output clock period is prolonged. Virtually any desired divider ratios can be implemented by means of further divider stages with divider D-type flip-flops of that kind and by virtue of a plurality of change-over switching operations.
It has been found that this circuit arrangement suffers from the disadvantage that, at high frequencies, there is a dependency of the function on the delay times which are internal to the circuit. Thus, the change-over switching signal can occur precisely at a time which is so unfavorable that metastable conditions are the consequence. In that case the circuit arrangement, after the occurrence of the change-over switching edge, cannot sufficiently rapidly decide which level is to be set.
In a static frequency divider with a divider ratio which can be switched over, with first and second divider D-type flip-flops which each have two inputs which can be activated alternately by way of control inputs, the object of the invention is to prevent the occurrence of metastable conditions and thus to ensure reliable operation up to extremely high frequencies. Finally the object of the invention is so to design the circuit arrangement that it can be implemented in all relevant technologies of semiconductor engineering.
In accordance with the invention that object is attained in that, in a static frequency divider with a divider ratio which can be switched over, including a first and a second divider D-type flip-flop each having two inputs which can be activated alternately by way of control inputs, successive synchronous D-type flip-flops are connected upstream of the two divider D-type flip-flops and the control inputs of the first and second divider D-type flip-flops are connected to separate change-over switching devices. Advantageously, the control inputs of the first and second divider D-type flip-flops are connected to separate control outputs of the successive synchronous D-type flip-flops. Preferably the control input of the first divider D-type flip-flop is connected to the control output of one of the successive synchronous D-type flip-flops and the control input of the second divider D-type flip-flop is connected to the control output of the preceding synchronous D-type flip-flop.
The teaching of the structure in accordance with the invention is based on the consideration that, in a synchronously cyclically controlled chain of D-type flip-flops, by means of the clock, it is possible to determine with a very high degree of accuracy when which xe2x80x9cmasterxe2x80x9d and when which xe2x80x9cslavexe2x80x9d of a D-type flip-flop is switched active. In that way the change-over switching action can be shifted precisely to the times at which it is certain that the occurrence of metastable conditions after the change-over switching operation is prevented. That is implemented by virtue of the fact that the first and second divider D-type flip-flops are switched over not at the same time but separately, more specifically in displaced relationship precisely by half an input clock period. In that case, the change-over switching action takes place in each case at a moment in time at which the input associated with that divider D-type flip-flop is not switched on.
The advantages of the structure according to the invention are essentially that virtually a doubling of the upper frequency limit that can be reached is achieved, while the power consumption or drain is approximately halved. When a power loss which is usual for the state of the art is demanded, approximately a doubling of the upper limit frequency which can be achieved would be possible. The circuit arrangement according to the invention can be carried into effect independently of the available technology, for example using CMOS, DMOS or bipolar designs.